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DATA SHEET
MOS INTEGRATED CIRCUITS
PD78F4938A
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The PD78F4938A is a product in the PD784938A Subseries in the 78K/IV Series. The PD78F4938A has flash memory in place of the internal ROM of the PD784938A. The flash memory incorporated enables program writing or erasing with the microcontroller mounted on the target board. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing.
PD784938A Subseries User's Manual Hardware: U13570E
78K/IV Series User's Manual Instructions: U10905E
FEATURES
* Pin-compatible with mask ROM version (except VPP pin) * Flash memory: 256 KB * Internal RAM: 10496 bytes 4 channels * Serial interface:
* UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator) * CSI (3-wire serial I/O): On-chip IEBusTM controller 2 channels
* * Supply voltage: VDD = 4.0 to 5.5 V (@12.58 MHz operation)
VDD = 3.0 to 5.5 V (@6.29 MHz operation)
APPLICATION
Car audio, etc.
ORDERING INFORMATION
Part Number Package 100-pin plastic QFP (14 x 20) Internal ROM 256 KB Internal RAM 10496 bytes
PD78F4938AGF-3BA
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U14118EJ1V0DS00 Date Published March 2001 N CP(K) Printed in Japan
(c)
2001 1999, 2001
PD78F4938A
78K/IV SERIES LINEUP
: Products in mass-production : Products under development Supports I2C bus Supports multimaster I2C bus
PD784038Y PD784038
PD784225Y PD784225
80-pin, ROM correction added Supports multimaster I2C bus
Standard models
PD784026
Enhanced A/D converter, 16-bit timer, and power management
Enhanced internal memory capacity Pin-compatible with the PD784026 Supports multimaster I2C bus
PD784216AY PD784216A
100-pin, enhanced I/O and internal memory capacity
PD784218AY PD784218A
Enhanced internal memory capacity, ROM correction added
PD784054 PD784046
ASSP models
PD784956A
For DC inverter control
On-chip 10-bit A/D converter
PD784967
Enhanced functions of the PD784938A, enhanced I/O and internal memory capacity. Enhanced peripheral functions
PD784938A
Enhanced functions of the PD784908, enhanced internal memory capacity, ROM correction added. Supports multimaster I2C bus
PD784908
On-chip IEBusTM controller
PD784928Y PD784915
Software servo control On-chip analog circuit for VCRs Enhanced timer
PD784928
Enhanced functions of the PD784915
PD784976A
On-chip VFD controller/driver
Remark
Although VFD (Vacuum Florescent Display is generally used, in some documents, the display is described as FIPTM (Florescent Inidicator Panel). VFD and FIP are functionally equivalent.
2
Data Sheet U14118EJ1V0DS
PD78F4938A
OVERVIEW OF FUNCTIONS
(1/2)
Part Number Item Number of basic instructions (mnemonics) 113 General-purpose registers Minimum instruction execution time 8 bits x 32 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory map) 320 ns/636 ns/1.27 s/2.54 s (@6.29 MHz operation) 160 ns/320 ns/636 ns/1.27 s (@12.58 MHz operation) 256 KB 10496 bytes 1 MB with program and data spaces combined Total Input I/O Pins with ancillary functionNote LED direct drive output Transistor direct drive N-ch open drain drive 80 pins 8 pins 72 pins 24 pins 8 pins 4 pins 4 bits x 2, or 8 bits x 1 Internal (simple version) Timer/event counter 0: Timer counter x 1 (16 bits) Capture register x 1 Compare register x 2 Timer/event counter 1: Timer counter x 1 (16 bits) Capture register x 1 Capture/compare register x 1 Compare register x 1 Timer/event counter 2: Timer counter x 1 (16 bits) Capture register x 1 Capture/compare register x 1 Compare register x 1 Timer 3 (16 bits): Timer counter x 1 Compare register x 1 Pulse output possible * Toggle output * PWM/PPG output * One-shot pulse output Real-time output port
PD78F4938A
Internal memory
ROM RAM
Memory space I/O port
Real-time output port IEBus controller Timer/counter
Pulse output possible * Toggle output * PWM/PPG output
Watch timer
Generates interrupt request at 0.5-second intervals (On-chip watch clock oscillator) Main clock (12.58 MHz) or watch clock (32.7 kHz) selectable as input clock Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16 (also usable as 1-bit output port) 12-bit resolution x 2 channels UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator) CSI (3-wire serial I/O): 2 channels 8-bit resolution x 8 channels 1 channel Internal (4 points of correction addresses can be set.) Provided (up to 1 MB)
Clock output PWM output Serial interface
A/D converter Watchdog timer ROM correction function External expansion function
Note
Pins with ancillary functions are included in the I/O pins.
Data Sheet U14118EJ1V0DS
3
PD78F4938A
(2/2)
Part Number Item Standby Interrupt Hardware source Software source Non-maskable Maskable HALT/STOP/IDLE mode 27 (internal: 20, external: 7 (sampling clock variable input: 1)) BRK instruction, BRKCS instruction, operand error Internal: 1, external: 1 Internal: 19, external: 6 Four programmable priority levels Three types of processing formats: Vectored interrupt/macro service/context switching Supply voltage * VDD = 4.0 to 5.5 V (@12.58 MHz operation) * VDD = 3.0 to 5.5 V (@6.29 MHz operation) 100-pin plastic QFP (14 x 20)
PD78F4938A
Package
4
Data Sheet U14118EJ1V0DS
PD78F4938A
CONTENTS
1. DIFFERENCES AMONG PRODUCTS IN PD784938A SUBSERIES ................................... 2. PIN CONFIGURATION (TOP VIEW) ........................................................................................... 3. BLOCK DIAGRAM ......................................................................................................................... 4. PIN 4.1 4.2 4.3 FUNCTIONS ............................................................................................................................ Port Pins ................................................................................................................................. Non-Port Pins ........................................................................................................................ Pin I/O Circuits and Recommended Connection of Unused Pins .................................
6 7 9 10 10 12 14
5. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) .................................................. 18 6. PROGRAMMING FLASH MEMORY ............................................................................................ 6.1 Selecting Communication Mode ......................................................................................... 6.2 Flash Memory Programming Functions ............................................................................ 6.3 Connecting Flashpro III ........................................................................................................ 19 19 20 21
7. ELECTRICAL SPECIFICATIONS .................................................................................................. 22 8. PACKAGE DRAWING .................................................................................................................... 42 9. RECOMMENDED SOLDERING CONDITIONS ........................................................................... 43 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 44 APPENDIX B. RELATED DOCUMENTS ........................................................................................... 47
Data Sheet U14118EJ1V0DS
5
PD78F4938A
1. DIFFERENCES AMONG PRODUCTS IN PD784938A SUBSERIES
The only difference between the PD784935A, 784936A, 784937A, and 784938A is the internal memory capacity. The PD78F4938A has a 256 KB flash memory in the place of the mask ROM of the above products. Table 11 shows the differences between these products. Table 1-1. Differences Among Products in PD784938A Subseries
Part Number Item Internal ROM 96 KB Mask ROM Internal RAM Regulator Electrical specifications Internal memory size switching registerNote IC pin VPP pin 5120 bytes Provided Refer to the data sheet of each product. None Provided 6656 bytes 8192 bytes 10496 bytes None 128 KB 192 KB 256 KB Flash memory
PD784935A
PD784936A
PD784937A
PD784938A
PD78F4938A
Provided None
None Provided
Note
The internal flash memory capacity and internal RAM capacity can be changed by using the internal memory size switching register (IMS).
Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version.
6
Data Sheet U14118EJ1V0DS
PD78F4938A
2. PIN CONFIGURATION (TOP VIEW)
* 100-pin plastic QFP (14 x 20)
PD78F4938AGF-3BA
P25/INTP4/ASCK/SCK1
P31/TxD/SO1
P23/INTP2/CI
P30/RxD/SI1
P26/INTP5
P24/INTP3
P22/INTP1
P21/INTP0
P32/SCK0
P36/T02 P37/T03 P100 P101 P102 P103 P104 P105/SCK3 P106/SI3 P107/SO3 RESET XT2 XT1 VSS X2 X1 REGOFF REGC VDD P00 P01 P02 P03 P04 P05 P06 P07 P67/REFRQ/HLDAK P66/WAIT/HLDRQ P65/WR
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P77/ANI7
P33/SO0
P35/TO1
P34/TO0
P20/NMI
P27/SI0
AVREF1
AVDD
AVSS
RX
TX
P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 VPP PWM1 PWM0 P17 P16 P15 P14/TxD2/SO2 P13/RxD2/SI2 P12/ASCK2/SCK2 P11 P10 ASTB/CLKOUT P90 P91 P92 P93 P94 P95 P96 P97 P40/AD0 P41/AD1 P42/AD2
P64/RD
P63/A19
P62/A18
P61/A17
P60/A16
P57/A15
P56/A14
P55/A13
P54/A12
VDD
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
Cautions 1. In normal operation mode, connect VPP pin directly to the VSS pin, or pull it down. In a system where the internal flash memory is rewritten while mounted on board, pull the VPP pin down. When pulling down, connection via a 470 or higher and 10 k or lower resistor is recommended. 2. Connect the AVDD pin directly to VDD. 3. Connect the AVSS pin directly to VSS.
Data Sheet U14118EJ1V0DS
P43/AD3
VSS
7
PD78F4938A
A8 to A19: AD0 to AD7: ANI0 to ANI7: ASCK, ASCK2: ASTB: AVDD: AVREF1: AVSS: CI: CLKOUT: HLDAK: HLDRQ: NMI: P00 to P07: P10 to P17: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P67: P70 to P77: P90 to P97: P100 to P107: Address bus Address/data bus Analog input Asynchronous serial clock Address strobe Analog power supply Reference voltage Analog ground Clock input Clock output Hold acknowledge Hold request Non-maskable interrupt Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 9 Port 10 PWM0, PWM1: Pulse width modulation output RD: REFRQ: REGC: REGOFF: RESET: RX: RxD, RxD2: SI0 to SI3: SO0 to SO3: TO0 to TO3: TX: TxD, TxD2: VDD: VPP: VSS: WAIT: WR: X1, X2: XT1, XT2: Read strobe Refresh request Regulator capacitance Regulator off Reset IEBus receive data Receive data Serial input Serial output Timer output IEBus transmit data Transmit data Power supply Programming power supply Ground Wait Write strobe Crystal (main system clock) Crystal (watch)
SCK0 to SCK3: Serial clock
INTP0 to INTP5: Interrupt from peripherals
8
Data Sheet U14118EJ1V0DS
PD78F4938A
3. BLOCK DIAGRAM
RxD/SI1 TxD/SO1 ASCK/SCK1
NMI INTP0 to INTP5
Programmable interrupt controller
UART/IOE 2 Baud-rate generator
INTP3 TO0 TO1
Timer/counter 0 (16 bits)
UART/IOE 1 Baud-rate generator
RxD2/SI2 TxD2/SO2 ASCK2/SCK2
INTP0
Timer/counter 1 (16 bits) Clocked serial interface
SCK0 SO0 SI0
INTP1 INTP2/CI TO2 TO3
Timer/counter 2 (16 bits)
78K/IV CPU core
Flash memory
SCK3 Clocked serial interface 3 SO3 SI3 Clock output ASTB/CLKOUT AD0 to AD7 A8 to A15 Bus I/F A16 to A19 RD WR WAIT/HLDRQ REFRQ/HLDAK P00 to P07
Timer 3 (16 bits)
P00 to P03 P04 to P07
Real-time output port
PWM0 PWM1
PWM
RAM Port 0
ANI0 to ANI7 AVDD AVREF1 AVSS INTP5 Port 3 TX IEBus controller RX RESET VPP X1 X2 REGC REGOFF VDD VSS XT1 Watch timer XT2 Port 10 P100 to P107 Port 4 P40 to P47 P30 to P37 A/D converter Port 2 P20 to P27 Port 1 P10 to P17
Port 5 System control (regulator)
P50 to P57
Watchdog timer
Port 6
P60 to P67
Port 7
P70 to P77
Port 9
P90 to P97
Data Sheet U14118EJ1V0DS
9
PD78F4938A
4. PIN FUNCTIONS 4.1 Port Pins (1/2)
Pin Name P00 to P07 I/O I/O Alternate Function -- Function Port 0 (P0): * 8-bit I/O port. * Can be used as real-time output port (4 bits x 2). * Input/output can be specified in 1-bit units. * An on-chip pull-up resistor can be specified by means of software for pins in input mode. * Can drive transistor. Port 1 (P1): * 8-bit I/O port. * Input/output can be specified in 1-bit units. * An on-chip pull-up resistor can be specified by means of software for pins in input mode. * Can drive LED.
P10 P11 P12 P13 P14 P15 to 17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 to P37 P40 to P47
I/O
-- -- ASCK2/SCK2 RxD2/SI2 TxD2/SO2 --
Input
NMI INTP0 INTP1 INTP2/CI INTP3 INTP4/ASCK/SCK1 INTP5 SI0
Port 2 (P2): * 8-bit input port. * P20 cannot be used as general-purpose port pin (non-maskable interrupt). However, input level can be checked by interrupt routine. * An on-chip pull-up resistor can be specified for P22 to P27 by means of software in 6-bit units. * P25/INTP4/ASCK/SCK1 pin operates as SCK1 I/O pin if so specified by CSIM1.
I/O
RxD/SI1 TxD/SO1 SCK0 SO0 TO0 to TO3
Port 3 (P3): * 8-bit I/O port. * Input/output can be specified in 1-bit units. * An on-chip pull-up resistor can be specified by means of software for pins in input mode. * P32 and P33 can be specified for N-ch open-drain connection. Port 4 (P4): * 8-bit I/O port. * Input/output can be specified in 1-bit units. * An on-chip pull-up resistor can be specified by means of software for pins in input mode. * Can drive LED. Port 5 (P5): * 8-bit I/O port. * Input/output can be specified in 1-bit units. * An on-chip pull-up resistor can be specified by means of software for pins in input mode. * Can drive LED. Port 6 (P6): * 8-bit I/O port. * Input/output can be specified in 1-bit units. * An on-chip pull-up resistor can be specified by means of software for pins in input mode.
I/O
AD0 to AD7
P50 to P57
I/O
A8 to A15
P60 to P63 P64 P65 P66 P67
I/O
A16 to A19 RD WR WAIT/HLDRQ REFRQ/HLDAK
10
Data Sheet U14118EJ1V0DS
PD78F4938A
4.1 Port Pins (2/2)
Pin Name P70 to P77 I/O I/O Alternate Function ANI0 to ANI7 Function Port 7 (P7): * 8-bit I/O port. * Input/output can be specified in 1-bit units. Port 9 (P9): * 8-bit I/O port. * Input/output can be specified in 1-bit units. * An on-chip pull-up resistor can be specified by means of software for pins in input mode. Port 10 (P10): * 8-bit I/O port. * Input/output can be specified in 1-bit units. * An on-chip pull-up resistor can be specified by means of software for pins in input mode. * P105 and P107 can be specified for N-ch open-drain connection.
P90 to P97
I/O
--
P100 to P104 P105 P106 P107
I/O SCK3 SI3 SO3
--
Data Sheet U14118EJ1V0DS
11
PD78F4938A
4.2 Non-Port Pins (1/2)
Pin Name TO0 to TO3 CI RxD RxD2 TxD TxD2 ASCK ASCK2 SI0 SI1 SI2 SI3 SO0 SO1 SO2 SO3 SCK0 SCK1 SCK2 SCK3 NMI INTP0 Input I/O Output Input Input Output I/O Output Input Input Alternate Function P34 to P37 P23/INTP2 P30/SI1 P13/SI2 P31/SO1 P14/SO2 P25/INTP4/SCK1 P12/SCK2 P27 P30/RxD P13/RxD2 P106 P33 P31/TxD P14/TxD2 P107 P32 P25/INTP4/ASCK P12/ASCK2 P105 P20 P21 Timer output Count clock input to timer/counter 2 Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data input (3-wire serial I/O0) Serial data input (3-wire serial I/O1) Serial data input (3-wire serial I/O2) Serial data input (3-wire serial I/O3) Serial data output (3-wire serial I/O0) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial data output (3-wire serial I/O3) Serial clock input/output (3-wire serial I/O0) Serial clock input/output (3-wire serial I/O1) Serial clock input/output (3-wire serial I/O2) Serial clock input/output (3-wire serial I/O3) External interrupt requests -- * Count clock input to timer/counter 1 * Capture trigger signal of CR11 or CR12 INTP1 P22 * Count clock input to timer/counter 2 * Capture trigger signal of CR22 INTP2 P23/CI * Count clock input to timer/counter 2 * Capture trigger signal of CR21 INTP3 P24 * Count clock input to timer/counter 0 * Capture trigger signal of CR02 INTP4 INTP5 AD0 to AD7 A8 to A15 A16 to A19 RD WR WAIT REFRQ HLDRQ HLDAK ASTB I/O Output Output Output Output Input Output Input Output Output P25/ASCK/SCK1 P26 P40 to P47 P50 to P57 P60 to P63 P64 P65 P66/HLDRQ P67/HLDAK P66/WAIT P67/REFRQ CLKOUT -- Conversion start trigger input of A/D converter Time-division address/data bus (external memory connection) Higher address bus (external memory connection) Higher address for address extension (external memory connection) Read strobe to external memory Write strobe to external memory Wait insertion Refresh pulse output to external pseudo-static memory Bus hold request input Bus hold acknowledge output Latch timing output of time-division address (A0 to A7) (when external memory is accessed) Function
12
Data Sheet U14118EJ1V0DS
PD78F4938A
4.2 Non-Port Pins (2/2)
Pin Name CLKOUT PWM0 PWM1 RX TX REGC I/O Output Output Output Input Output -- Alternate Function ASTB -- -- -- -- -- Clock output PWM output 0 PWM output 1 Data input (IEBus) Data output (IEBus) Connecting capacitor for regulation output stabilization/power supply when regulator is stopped REGOFF RESET X1 X2 XT1 XT2 ANI0 to ANI7 AVREF1 AVDD AVSS VDD VSS VPP Input -- Input Input -- Input -- Input -- -- -- P70 to P77 -- Analog voltage input for A/D converter Application of reference voltage for A/D converter Positive power supply for A/D converter GND for A/D converter Positive power supply GND Sets flash memory programming mode. For high voltage application when program is written or verified. In normal operation mode, connect VPP pin directly to the VSS pin, or pull it down. In a system where the internal flash memory is rewritten while mounted on board, pull the VPP pin down. When pulling down, connection via a 470 or higher and 10 k or lower resistor is recommended. -- -- -- Regulator operation specification signal Chip reset Connecting crystal resonator for system clock oscillation (clock can be also input to X1.) Watch clock connection Function
Data Sheet U14118EJ1V0DS
13
PD78F4938A
4.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 4-1. For the I/O circuit configuration of each type, refer to Figure 4-1. Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (1/2)
Pin Name P00 to P07 P10, P11 P12/ASCK2/SCK2 P13/RxD2/SI2 P14/TxD2/SO2 P15 to P17 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 8-A I/O Input: Connect to VDD. Output: Leave open. P26/INTP5 P27/SI0 P30/RxD/SI1 P31/TxD/SO1 P32/SCK0 P33/SO0 P34/TO0 to P37/TO3 P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0 to P77/ANI7 P90 to P97 P100 to P104 P105/SCK3 P106/SI3 P107/SO3 ASTB/CLKOUT RESET VPP XT2 XT1 10-A 8-A 10-A 4 2 1 -- -- -- Input Output Input Connect directly to VSS. Leave open. Connect directly to VSS. Leave open. -- 20 5-A I/O Input: Connect to VDD or VSS. Output: Leave open. 5-A 10-A 5-A I/O Input: Connect to VDD. Output: Leave open. 2-A Input Connect to VDD. 2-A Connect to VDD. 2 Input Connect to VDD or VSS. 8-A 5-A 5-A I/O Circuit Type I/O I/O Recommended Connection of Unused Pins Input: Connect to VDD. Output: Leave open.
14
Data Sheet U14118EJ1V0DS
PD78F4938A
Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2)
Pin Name REGOFF REGC PWM0, PWM1 RX TX AVREF1 AVSS AVDD Connect to VDD. 3 1 3 -- 1 -- I/O Circuit Type I/O -- -- Output Input Output -- Recommended Connection of Unused Pins Connect directly to VDD. Connect to VDD. Leave open. Connect to VDD or VSS. Leave open. Connect to VSS.
Caution Connect an I/O pin to VDD via a resistor of several 10 k if the I/O mode of the pin is unstable (especially if the voltage on the reset pin is higher than the low-level input voltage on power application or if the mode is changed between input and output by software). Remark The circuit type numbers are common for the 78K Series and are not always sequential for one product (some circuits are not provided).
Data Sheet U14118EJ1V0DS
15
PD78F4938A
Figure 4-1. Pin I/O Circuits (1/2)
Type 1 Type 4 VDD VDD P IN N Output disable N Data P OUT
Push-pull output that can go into a high-impedance state (both P-ch and N-ch are off). Type 2
Type 5-A
VDD
Pull-up enable Data IN Output disable Input enable Type 8-A
P VDD P IN/OUT N
Schmitt-triggered input with hysteresis characteristics
Type 2-A VDD
VDD
Pull-up enable P Pull-up enable Data
P VDD P IN/OUT
IN
Output disable
N
Schmitt-triggered input with hysteresis characteristics
Type 3
Type 10-A
VDD
VDD P-ch Data N-ch OUT
Pull-up enable VDD Data P
P
IN/OUT Open-drain Output disable N
16
Data Sheet U14118EJ1V0DS
PD78F4938A
Figure 4-1. Pin I/O Circuits (2/2)
Type 20 Data
VDD P IN/OUT
Output disable Comparator P N
N
+ -
VREF (threshold voltage) Input enable
Data Sheet U14118EJ1V0DS
17
PD78F4938A
5. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
IMS is a register to prevent a certain part of the internal memory from being used by software. By setting the IMS, it is possible to establish a memory map that is the same as that of mask ROM version with a different internal memory (ROM, RAM) capacity. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to FFH. Figure 5-1. Internal Memory Size Switching Register (IMS) Format
Address Symbol IMS 0FFFCH 7 1 After reset FFH 6 1 5 ROM1 W 4 ROM0 3 1 2 1 1 RAM1 0 RAM0
ROM1 0 0 1 1
ROM0 0 1 0 1 256 KB 96 KB 128 KB 192 KB
Internal ROM Capacity Selection
RAM1 0 0 1 1
RAM0 0 1 0 1
Internal RAM Capacity Selection 10496 bytes 5120 bytes 6656 bytes 8192 bytes
Caution IMS is not available for mask ROM versions (PD784935A, 784936A, 784937A, and 784938A). The IMS settings to create the same memory map as mask ROM versions are shown in Table 5-1. Table 5-1. Internal Memory Size Switching Register (IMS) Settings
Relevant Mask ROM Version IMS Setting DDH EEH FFH CCH
PD784935A PD784936A PD784937A PD784938A
Note
Shifting to the flash memory programming mode sets all pins not used for flash memory programming to the same state as immediately after reset. Therefore, if the external devices do not acknowledge the port state immediately after reset, handling such as connecting to VDD via a resistor or connecting to VSS via a resistor is required.
18
Data Sheet U14118EJ1V0DS
PD78F4938A
6. PROGRAMMING FLASH MEMORY
Flash memory can be written while mounted on the target system (on-board writing). Connect the dedicated flash programmer (Flashpro III (part No.: FL-PR3, PG-FP3)) to the host machine and target system for programming. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro III. Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd. 6.1 Selecting Communication Mode The Flashpro III is used to write data into a flash memory by serial communications. Select the communication mode for writing from Table 6-1. Figure 6-1 shows the format used to select the communication mode. Each communication mode is selected with the number of VPP pulses shown in Table 6-1. Table 6-1. Communication Mode
Communication Mode 3-wire serial I/O Number of Channels 3 Pins Used SCK3/P105 SI3/P106 SO3/P107 SCK0/P32 SI0/P27 SO0/P33 SCK3/P105 SI3/P106 SO3/P107 P104 (for handshake) UART 1 RxD/P30 TxD/P31 Number of VPP Pulses 1
0
3
8
Caution Always select the communication mode using the number of VPP pulses shown in Table 6-1. Figure 6-1. Communication Mode Selection Format
VPP pulses 10 V VPP VDD VSS VDD RESET VSS Flash memory write mode 1 2 n
Data Sheet U14118EJ1V0DS
19
PD78F4938A
6.2 Flash Memory Programming Functions
By transmitting and receiving various commands and data by the selected communication mode, operations such as writing to the flash memory are performed. Table 6-2 shows the major functions. Table 6-2. Flash Memory Programming Functions
Function Area erase Area blank check Data write Description Erase the contents of the specified memory area where one memory block is 16 KB. Checks the erase state of the specified area. Writes to the flash memory based on the start write address and the number of data written (number of bytes). Compares the data input with the contents of the specified memory area.
Area verify
Verification for the flash memory entails supplying the data to be verified from an external source via a serial interface, and then outputting the existence of unmatched data to the external source after referencing the areas or all of the data. Consequently, the flash memory is not equipped with a read function, and it is not possible for third parties to read the contents of the flash memory with the use of the verification function.
20
Data Sheet U14118EJ1V0DS
PD78F4938A
6.3 Connecting Flashpro III
The connection between the Flashpro III and the PD78F4938A differs depending on the communication mode (3-wire serial I/O or UART). Figures 6-2 and 6-3 are the connection diagrams in each case. Figure 6-2. Flashpro III Connection in 3-Wire Serial I/O Mode
Flashpro III VPP VDD RESET SCK SO SI HS VSS
PD78F4938A
VPP VDD RESET SCK SI SO P104Note VSS
Note
Only in the handshake communication Figure 6-3. Flashpro III Connection in UART Mode
Flashpro III VPP VDD RESET SO SI VSS
PD78F4938A
VPP VDD RESET RxD TxD VSS
Data Sheet U14118EJ1V0DS
21
PD78F4938A
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD AVDD AVSS AVREF1 Input voltage Analog input voltage Output voltage Output current, low VI2 VIAN VO IOL Per pin Total for all pins of ports 0, 3, 6, 10 and P54 to P57 Total for all pins of ports 1, 4, 7, 9, P50 to P53, PWM0, PWM1, and TX pins Output current, high IOH Per pin Total for all pins of ports 0, 3, 6, 10,and P54 to P57 Total for all pins of ports 1, 4, 7, 9, P50 to P53, PWM0, PWM1, and TX pins Operating ambient temperature Storage temperature TA Tstg -30 mA C C Analog input voltage A/D converter reference voltage input Conditions Ratings -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to VSS + 0.3 -0.3 to VDD + 0.3 -0.3 to +10.5 AVSS - 0.3 to AVREF1 + 0.3 -0.3 to VDD + 0.3 10 50 Unit V V V V V V V mA mA
50
mA
-6 -30
mA mA
-40 to +85 -40 to +150
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
22
Data Sheet U14118EJ1V0DS
PD78F4938A
Operating Conditions * Clock frequency
Clock Frequency 4 MHz fXX 12.58 MHz 4 MHz fXX 6.29 MHz Supply Voltage 4.0 VDD 5.5 V 3.0 VDD 5.5 V
* Operating ambient temperature (TA): -40 to +85C * Power supply voltage and clock cycle time: Refer to Figure 7-1 * Selection of internal regulator operation (REGOFF pin: low-level input) Figure 7-1. Power Supply Voltage and Clock Cycle Time
10000
2000
1/8 of fXX = 2 MHz
Clock cycle time tCYK [ns]
1000 Guaranteed operation range 500
200 159 100 79 fXX = 12.58 MHz undivided fXX = 6.29 MHz undivided
0
0
1
2
3
4
5
6
Power supply voltage [V]
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V. Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
Data Sheet U14118EJ1V0DS
23
PD78F4938A
Main Oscillator Characteristics (TA = -40 to +85C, VDD = 3.0 to 5.5 V, VSS = 0 V)
Parameter Oscillator frequency Symbol fXX Conditions Ceramic resonator or recommended resonator 4.0 VDD 5.5 V 3.0 VDD 5.5 V MIN. 4.0 4.0 MAX. 12.58 6.29 Unit MHz MHz
Caution When using the main clock oscillator, wire as follows to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Remarks 1. Connect a 12.582912 MHz or 6.291456 MHz oscillator to operate the internal clock timer with the main clock. 2. For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 3.0 to 5.5 V, VSS = 0 V)
Parameter Oscillator frequency Oscillation stabilization time Symbol fXT fsxt Conditions Ceramic resonator or crystal resonator 4.5 VDD 5.5 V MIN. 32 TYP. 32.768 1.2 MAX. 35 2 10 Oscillation hold voltage Watch timer operating voltage VDDXT VDDW 3.0 3.0 5.5 5.5 Unit kHz s s V V
24
Data Sheet U14118EJ1V0DS
PD78F4938A
DC Characteristics (TA = -40 to +85C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (1/2)
Parameter Input voltage, lowNote Symbol VIL1 Conditions P10, P11, P13 to P17, P30, P31, P34 to P37, P70 to P77, P90 to P97, P100 to P104, X1, X2, XT1, XT2 P12, P20 to P27, P32, P33, P105 to P107 RESET P00 to P07, P40 to P47, 4.5 VDD 5.5 V P50 to P57, P60 to P67 P10, P11, P13 to P17, P30, P31, P34 to P37, P70 to P77, P90 to P97, P100 to P104, X1, X2, XT1, XT2 P12, P20 to P27, P32, P33, P105 to P107 RESET P00 to P07, P40 to P47, 4.5 VDD 5.5 V P50 to P57, P60 to P67 IOL = 20 A IOL = 100 A IOL = 2 mA VOL2 IOL = 8 mA, P10 to P17, 4.5 VDD 5.5 V P40 to P47, P50 to P57 IOH = -20 A IOL = -100 A IOL = -2 mA VOH2 VDD-0.1 VDD-0.2 VDD-1.0 MIN. -0.3 TYP. MAX. 0.3VDD Unit V
VIL2
-0.3
0.2VDD
V
VIL3 VIL4 Input voltage, high VIH1
-0.3 -0.3 0.7VDD
0.8 0.2VDD VDD+0.3
V V V
VIH2
0.8VDD
VDD+0.3
V
VIH3 VIH4 Output voltage, low VOL1
2.2 0.7VDD
VDD+0.3 0.3VDD 0.1 0.2 0.4 1.0
V V V V V V
Output voltage, high
VOH1
V V V V
IOL = -5 mA, 4.5 V VDD 5.5 V VDD-2.4 P10 to P17, P40 to P47, P50 to P57 VIN = 0 V For pins other than X1, X2, XT1, and XT2 X1, X2, XT1, XT2 VIN = VDD For pins other than X1, X2, XT1, and XT2 X1, X2, XT1, XT2 VOUT = 0 V VOUT = VDD 10
Input leakage current, low
ILIL1
A A A A A A
ILIL2 Input leakage current, high ILIH1
-20 10
ILIH2 Output leakage current, low Output leakage current, high ILOL1 ILOH1
20 -10 10
Note
These values are valid when the pull-up resistor is off.
Data Sheet U14118EJ1V0DS
25
PD78F4938A
DC Characteristics (TA = -40 to +85C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (2/2)
Parameter Power supply current Symbol IDD1 Operating mode Conditions fXX = 12.58 MHz, 4.0 V VDD 5.5 V fXX = 6.29 MHz, 3.0 V VDD 5.5 V IDD2 HALT mode fXX = 12.58 MHz, when peripheral clock stopsNote, 4.0 V VDD 5.5 V fXX = 6.29 MHz, when peripheral clock stopsNote, 3.0 V VDD 5.5 V IDD3 IDLE mode fXX = 12.58 MHz, 4.0 VDD 5.5 V fXX = 6.29 MHz, 3.0 V VDD 5.5 V Data hold voltage Data hold current VDDDR IDDDR STOP mode STOP mode VDD = 2.5 V, subsystem clock stops VDD = 5.5 V, subsystem clock stops Pull-up resistor RL VIN = 0 V 15 2.5 4 MIN. TYP. 19 MAX. 38 Unit mA
10
20
mA
3
6
mA
1.8
3.6
mA
2
4
mA
1
2
mA
5.5 20
V
A A
k
20
100
40
80
Note
When the main system clock: fCLK = fXX/8 is selected (set by the standby control register (STBC)) and the watch timer is operating.
Remark These values are valid when the internal regulator is on (REGOFF pin = low-level input).
26
Data Sheet U14118EJ1V0DS
PD78F4938A
AC Characteristics (TA = -40 to +85C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (1) Read/write operation (1/2)
Parameter Cycle time Symbol tCYK Conditions 4.0 VDD 5.5 V VDD = 3.0 V Address setup time (to ASTB) Address hold time (from ASTB) ASTB high-level width tWSTH tHSTLA tSAST VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V Address hold time (from RD) tHRA VDD = 5.0 V VDD = 3.0 V Delay time from address to RD Address float time (from RD) Data input time from address tFAR tDAID VDD = 5.0 V VDD = 3.0 V Data input time from ASTB tDSTID VDD = 5.0 V VDD = 3.0 V Data input time from RD tDRID VDD = 5.0 V VDD = 3.0 V Delay time from ASTB to RD Data hold time (from RD) Address active time from RD tHRID tDRA VDD = 5.0 V VDD = 3.0 V Delay time from RD to ASTB RD low-level width tWRL tDRST VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V tDSTR VDD = 5.0 V VDD = 3.0 V 0.5T-9 0.5T-9 0 0.5T-2 0.5T-12 0.5T-9 0.5T-9 (1.5+n) T-25 (1.5+n) T-30 tDAR VDD = 5.0 V VDD = 3.0 V MIN. 79 159 (0.5+a) T-11 (0.5+a) T-15 0.5T-19 0.5T-24 (0.5+a) T-17 (0.5+a) T-40 0.5T-14 0.5T-14 (1+a) T-5 (1+a) T-10 0 (2.5+a+n) T-37 (2.5+a+n) T-52 (2+n) T-35 (2+n) T-50 (1.5+n) T-40 (1.5+n) T-50 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T: tCYK = 1/fCLK (fCLK: internal system clock) 2. a: 1 during address wait; otherwise 0 3. n: Number of wait states (n 0) 4. Calculated as T = 79 ns (min.) @ VDD = 5.0 V 5. Calculated as T = 159 ns (min.) @ VDD = 3.0 V
Data Sheet U14118EJ1V0DS
27
PD78F4938A
AC Characteristics (TA = -40 to +85C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (1) Read/write operation (2/2)
Parameter Delay time from address to WR Address hold time (from WR) tHWA Symbol tDAW Conditions VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V Delay time from ASTB to data output Data output time from WR Delay time from ASTB to WR Data setup time (to WR) tSODWR tDWOD tDSTW VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V Data hold time (from WR) tHWOD VDD = 5.0 V VDD = 3.0 V Delay time from WR to ASTB WR low-level width tWWL tDWST VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V 0.5T-9 0.5T-9 (1.5+n) T-20 (1.5+n) T-25 0.5T-14 0.5T-14 0.5T-9 0.5T-9 (1.5+n) T-25 (1.5+n) T-30 tDSTOD VDD = 5.0 V VDD = 3.0 V MIN. (1+a) T-5 (1+a) T-10 0.5T-14 0.5T-14 0.5T+15 0.5T+20 15 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T: tCYK = 1/fCLK (fCLK: internal system clock) 2. a: 1 during address wait; otherwise 0 3. n: Number of wait states (n 0) 4. Calculated as T = 79 ns (min.) @ VDD = 5.0 V 5. Calculated as T = 159 ns (min.) @ VDD = 3.0 V
28
Data Sheet U14118EJ1V0DS
PD78F4938A
AC Characteristics (TA = -40 to +85C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (2) External wait timing
Parameter WAIT input time from address WAIT input time from ASTB tDSTWT Symbol tDAWT Conditions VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V WAIT hold time from ASTB tHSTWTH VDD = 5.0 V VDD = 3.0 V Delay time from ASTB to WAIT WAIT input time from RD tDRWTL tDSTWTH VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V WAIT hold time from RD tHRWT VDD = 5.0 V VDD = 3.0 V Delay time from RD to WAIT Data input time from WAIT tDWTID tDRWTH VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V Delay time from WAIT to RD Delay time from WAIT to WR WAIT input time from WR tDWWTL tDWTW tDWTR VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V WAIT hold time from WR tHWWT VDD = 5.0 V VDD = 3.0 V Delay time from WR to WAIT tDWWTH VDD = 5.0 V VDD = 3.0 V nT+5 nT+10 (1+n) T-40 (1+n) T-60 0.5T 0.5T 0.5T 0.5T T-40 T-60 nT+5 nT+10 (1+n) T-40 (1+n) T-60 0.5T-5 0.5T-10 (0.5+n) T+5 (0.5+n) T+10 (1.5+a) T-40 (1.5+a) T-60 T-40 T-60 MIN. TYP. MAX. (2+a) T-40 (2+a) T-60 1.5T-40 1.5T-60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T: tCYK = 1/fCLK (fCLK: internal system clock) 2. a: 1 during address wait; otherwise 0 3. n: Number of wait states (n 0) 4. Calculated as T = 79 ns (min.) @ VDD = 5.0 V 5. Calculated as T = 159 ns (min.) @ VDD = 3.0 V
Data Sheet U14118EJ1V0DS
29
PD78F4938A
AC Characteristics (TA = -40 to +85C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (3) Bus hold/refresh timing
Parameter Delay time from HLDRQ to float Delay time from HLDRQ to HLDAK Delay time from float to HLDAK Delay time from HLDRQ to HLDAK Delay time from HLDAK to active Random read/write cycle time tRC tDHAC tDHQLHAL tDCFHA tDHQHHAH Symbol tFHQC Conditions VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V REFRQ low-level pulse width tWRFQL VDD = 5.0 V VDD = 3.0 V Delay time from ASTB to REFRQ Delay time from RD to REFRQ Delay time from WR to REFRQ Delay time from REFRQ to ASTB REFRQ high-level pulse width tWRFQH tDRFQST tDWRFQ tDRRFQ tDSTRFQ VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V T-20 T-30 3T 3T 1.5T-25 1.5T-30 0.5T-9 0.5T-9 1.5T-9 1.5T-9 1.5T-9 1.5T-9 0.5T-9 0.5T-9 1.5T-25 1.5T-30 MIN. TYP. MAX. (2+4+a+n) T+50 (2+4+a+n) T+50 (3+4+a+n) T+30 (3+4+a+n) T+40 T+30 T+30 2T+40 2T+60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T: tCYK = 1/fCLK (fCLK: internal system clock) 2. a: 1 during address wait; otherwise 0 3. n: Number of wait states (n 0) 4. Calculated as T = 79 ns (min.) @ VDD = 5.0 V 5. Calculated as T = 159 ns (min.) @ VDD = 3.0 V
30
Data Sheet U14118EJ1V0DS
PD78F4938A
Timing Waveform (1) Read operation
tWSTH ASTB tSAST tHSTLA A8 to A19 tDSTID tDRST
tDAID AD0 to AD7 tDSTR tDAR RD tWRL tFRA tDRID
tHRA
tHRID tDRA
(2) Write operation
tWSTH ASTB tSAST tHSTLA A8 to A19 tDSTOD tDWST
tHWA AD0 to AD7 tDSTW tDAW WR tWWL tDWOD tSODWR tHWOD
Data Sheet U14118EJ1V0DS
31
PD78F4938A
Hold Timing
ASTB, A8 to A19, AD0 to AD7, RD, WR tFHQC HLDRQ tDHQHHAH HLDAK tDHQLHAL tDCFHA tDHAC
External Wait Signal Input Timing (1) Read operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8 to A19
AD0 to AD7 tDAWT RD tDRWTL WAIT tHRWT tDRWTH tDWTR tDWTID
(2) Write operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8 to A19
AD0 to AD7 tDAWT WR tDWWTL WAIT tHWWT tDWWTH tDWTW
32
Data Sheet U14118EJ1V0DS
PD78F4938A
Refresh Timing Waveform (1) Random read/write cycle
tRC ASTB
WR tRC RD tRC tRC tRC
(2) When refresh memory is accessed for a read and write at the same time
ASTB
RD, WR tDSTRFQ tDRFQST tWRFQH
REFRQ tWRFQL
(3) Refresh after a read
ASTB tDRFQST RD tDRRFQ REFRQ tWRFQL
(4) Refresh after a write
ASTB tDRFQST WR tDWRFQ REFRQ tWRFQL
Data Sheet U14118EJ1V0DS
33
PD78F4938A
Serial Operation (TA = -40 to +85C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (a) CSI0, CSI3 3-wire serial I/O mode (SCK0, SCK3 ... External clock input)
Parameter SCK cycle time (SCK0, SCK3) SCK low-level width (SCK0, SCK3) SCK high-level width (SCK0, SCK3) SI0, SI3 setup time (to SCK0, SCK3) SI0, SI3 hold time (from SCK0, SCK3) Delay time from SCK0, SCK3 to output SO0, SO3 output hold time (from SCK0, SCK3) Symbol tCYSK0, tCYSK3 tWSKL0, tWSKL3 tWSKH0, tWSKH3 tSSSK0, tSSSK3 tHSSK0, tHSSK3 tDBSK0, tDBSK3 tHSBSK0, tHSBSK3 CMOS output N-ch open-drain output (RL = 1 k) When data is transferred Conditions SO0 and SO3 are CMOS outputs SO0 and SO3 are CMOS outputs SO0 and SO3 are CMOS outputs fCLK = fXX Except fCLK = fXX fCLK = fXX Except fCLK = fXX fCLK = fXX Except fCLK = fXX MIN. 8/fXX 4/fCLK 4/fXX - 40 2/fCLK - 40 4/fXX - 40 2/fCLK - 40 80 MAX. Unit ns ns ns ns ns ns ns
1/fCLK + 80
ns
0 0 0.5tCYSK0 - 40, 0.5tCYSK3 - 40
1/fCLK + 150 1/fCLK + 400
ns ns ns
Remarks 1. The values in this table are those when CL = 100 pF. 2. fXX: External oscillator frequency (fXX = 12.58 MHz or fXX = 6.29 MHz) 3. fCLK: System clock oscillation frequency (selectable from fXX, fXX/2, fXX/4, and fXX/8 by the standby control register (STBC)) (b) CSI0, CSI3 3-wire serial I/O mode (SCK0, SCK3 ... Internal clock output)
Parameter SCK cycle time (SCK0, SCK3) SCK low-level width (SCK0, SCK3) SCK high-level width (SCK0, SCK3) SI0, SI3 setup time (to SCK0, SCK3) SI0, SI3 hold time (from SCK0, SCK3) Delay time from SCK0, SCK3 to output SO0, SO3 output hold time (from SCK0, SCK3) Symbol tCYSK0, tCYSK3 tWSKL0, tWSKL3 tWSKH0, tWSKH3 tSSSK0, tSSSK3 tHSSK0, tHSSK3 tDBSK0, tDBSK3 tHSBSK0, tHSBSK3 CMOS output N-ch open-drain output (RL = 1 k) When data is transferred Conditions SO0 and SO3 are CMOS outputs SO0 and SO3 are CMOS outputs SO0 and SO3 are CMOS outputs Except fCLK = fXX/8 fCLK = fXX/8 Except fCLK = fXX/8 fCLK = fXX/8 Except fCLK = fXX/8 fCLK = fXX/8 MIN. 8/fXX 16/fXX 4/fXX - 40 8/fXX - 40 4/fXX - 40 8/fXX - 40 80 MAX. Unit ns ns ns ns ns ns ns
80
ns
0 0 0.5tCYSK0 - 40, 0.5tCYSK3 - 40
150 400
ns ns ns
Remarks 1. The values in this table are those when CL = 100 pF. 2. fXX: External oscillator frequency (fXX = 12.58 MHz or fXX = 6.29 MHz) 3. fCLK: System clock oscillation frequency (selectable from fXX, fXX/2, fXX/4, and fXX/8 by the standby control register (STBC))
34
Data Sheet U14118EJ1V0DS
PD78F4938A
Serial Operation (TA = -40 to +85C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (c) UART0, UART3 (Asynchronous serial interface mode)
Parameter ASCK0, ASCK2 cycle time Symbol tCYASK Conditions 4.0 VDD 5.5 V MIN. 160 320 ASCK0, ASCK2 low-level width tWASKL 4.0 VDD 5.5 V 65 120 ASCK0, ASCK2 high-level width tWASKH 4.0 VDD 5.5 V 65 120 TYP. MAX. Unit ns ns ns ns ns ns
Data Sheet U14118EJ1V0DS
35
PD78F4938A
Serial Operation (TA = -40 to +85C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V) (d) IOE1, IOE2 3-wire serial I/O mode (SCK1, SCK2 ... External clock input)
Parameter SCK cycle time (SCK1, SCK2) Symbol tCYSK1 tCYSK2 SCK low-level width (SCK1, SCK2) SCK high-level width (SCK1, SCK2) SI1, SI2 setup time (to SCK1, SCK2) SI1, SI2 hold time (from SCK1, SCK2) Delay time from SCK1, SCK2 to output SO1, SO2 output hold time (from SCK1, SCK2) tWSKL1, tWSKL2 tWSKH1, tWSKH2 tSSSK1, tSSSK2 tHSSK1, tHSSK2 tDSOSK1, tDSOSK2 tHSOSK1, tHSOSK2 When data is transferred 4.0 VDD 5.5 V 4.0 VDD 5.5 V Conditions 4.0 VDD 5.5 V MIN. 640 1280 280 600 280 600 40 MAX. Unit ns ns ns ns ns ns ns
40
ns
0
50
ns
0.5tCYSK1 - 40, 0.5tCYSK2 - 40
ns
Remarks 1. The values in this table are those when CL = 100 pF. 2. T: Selected serial clock cycle. The minimum value is 8/fXX. (e) IOE1, IOE2 3-wire serial I/O mode (SCK1, SCK2 ... Internal clock output)
Parameter SCK cycle time (SCK1, SCK2) Symbol tCYSK1 tCYSK2 tWSKL1, tWSKL2 tWSKH1, tWSKH2 tSSSK1, tSSSK2 tHSSK1, tHSSK2 tDSOSK1, tDSOSK2 tHSOSK1, tHSOSK2 When data is transferred Conditions MIN. T MAX. Unit ns
SCK low-level width (SCK1, SCK2) SCK high-level width (SCK1, SCK2) SI1, SI2 setup time (to SCK1, SCK2) SI1, SI2 hold time (from SCK1, SCK2) Delay time from SCK1, SCK2 to output SO1, SO2 output hold time (from SCK1, SCK2)
0.5T - 40
ns
0.5T - 40
ns
40
ns
40
ns
0
50
ns
0.5tCYSK1 - 40, 0.5tCYSK2 - 40
ns
Remarks 1. The values in this table are those when CL = 100 pF. 2. T: Selected serial clock cycle. The minimum value is 8/fXX.
36
Data Sheet U14118EJ1V0DS
PD78F4938A
Other Operations (TA = -40 to +85C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V)
Parameter NMI high-/low-level width Symbol tWNIL tWNIH tWIT0L tWIT0H tWIT1L tWIT1H tWIT2L tWIT2H tWRSL tWRSH Conditions MIN. 10 TYP. MAX. Unit
s
s
INTP0 high-/low-level width
4tCYSMP
INTP1 to INTP3, CI high-/ low-level width INTP4, INTP5 high-/ low-level width RESET high-/low-level widthNote
4tCYCPU
s
10
s s
10
Note
When the power is turned on or when STOP mode is released by reset, secure the oscillation stabilization wait time while the RESET is at a low-level width. When the power is applied, be sure to activate VDD in the RESET = low-level state.
Remark tCYSMP: Sampling clock set by software tCYCPU: CPU clock set by software in the CPU Clock Output Operation (TA = -40 to +85C, VDD = AVDD = 3.0 to 5.5 V, VSS = AVSS = 0 V)
Parameter CLKOUT cycle time CLKOUT low-level width Symbol tCYCL tCLL nT 4.5 VDD 5.5 V Conditions MIN. 79 0.5T - 10 0.5T - 20 CLKOUT high-level width tCLH 4.5 VDD 5.5 V 0.5T - 10 0.5T - 20 CLKOUT rise time tCLR 4.5 VDD 5.5 V 3.0 VDD 4.5 V CLKOUT fall time tCLF 4.5 VDD 5.5 V 3.0 VDD 4.5 V 10 20 10 20 TYP. MAX. 32000 Unit ns ns ns ns ns ns ns ns ns
Remark n: Division ratio of clock output frequency, T: tCYK = 1/fCLK (system clock cycle time) IEBus Controller Characteristics (TA = -40 to +85C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter IEBus system clock frequency Symbol fs Mode 1 Conditions MIN. TYP. 6.29 MAX. Unit MHz
Remark Although the system clock frequency in the IEBus specifications is 6.0 MHz, in the PD784938A, operation at 6.29 MHz is also guaranteed. Note, however, that operation at 6.0 MHz and 6.29 MHz cannot be used together.
Data Sheet U14118EJ1V0DS
37
PD78F4938A
A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = AVREF1 = 3.0 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Overall errorNote 1 IEAD = 00H 6.29 MHz fXX 12.58 MHz and other than FR = 1 6.29 MHz fXX 12.58 MHz and FR = 1 IEAD = 01H 4.5 VDD 5.5 V 3.0 VDD < 5.5 V Quantization error Conversion time tCONV FR = 1: 120tCYK FR = 0: 240tCYK Sampling time tSAMP FR = 1: 18tCYK FR = 0: 36tCYK Analog input voltage Analog input impedance Reference voltage AVREF1 resistor AVREF1 current AVDD current VIAN RAN AVREF1 RAVREF1 AIREF1 AIDD1 AIDD2 3.0 3.0 10 0.5 2.0 1.5 5.0 20 9.5 19.1 1.4 2.9 AVSS 1000 AVDD 1 1.4 Symbol Conditions MIN. 8 0.6 1.5 2.2 2.6 1/2 480 960 72 144 AVREF1 TYP. MAX. Unit bit %FSRNote 2 %FSRNote 2 %FSRNote 2 %FSRNote 2 LSB
s s s s
V M V k mA mA mA
Notes 1. Excludes quantization error (1/2 LSB). 2. It is indicated as a ratio (%FSR) to the full-scale value. Caution The analog input pins of the PD78F4938A function alternately as the port 7 pins (I/O port pins). However when using the A/D converter, it is necessary to set all the pins of port 7 to input mode in order to prevent data from being inverted by the output port operation, thus degrading the A/D conversion accuracy. At this time, pins cannot be used as output ports even though they are not used as A/D analog input port.
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Data Sheet U14118EJ1V0DS
PD78F4938A
Serial Operation (CSI, CSI3)
tWSKLn SCK0, SCK3 tCYSKn SI0, SI3 tDSBSKn SO0, SO3 tHSBSKn tSSSKn tHSSKn Input data tWSKHn
Output data
n = 0, 3 Serial Operation (IOE1, IOE2)
tWSKL1 SCK1, SCK2 tCYSK1 SI1, SI2
tWSKH1
tSSSK1
tHSSK1
Input data tDSOSK tHSOSK
SO1, SO2
Output data
Serial Operation (UART0, UART2)
tWASKH
tWASKL
ASCK0, ASCK2 tCYASK
Clock Output Timing
tCLH
tCLL
CLKOUT tCLR tCYCL tCLF
Data Sheet U14118EJ1V0DS
39
PD78F4938A
Interrupt Request Input Timing
tWNIH
tWNIL
NMI
tWIT0H
tWIT0L
INTP0
tWIT1H
tWIT1L
CI, INTP1 to INTP3
tWIT2H
tWIT2L
INTP4, INTP5
Reset Input Timing
tWRSH
tWRSL
RESET
40
Data Sheet U14118EJ1V0DS
PD78F4938A
Data Retention Characteristics
STOP mode setting
VDD tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
NMI (Clearing by falling edge)
NMI (Clearing by rising edge)
Data Sheet U14118EJ1V0DS
41
PD78F4938A
8. PACKAGE DRAWING
100PIN PLASTIC QFP (14x20)
A B
80 81
51 50
detail of lead end CD
S Q R
100 1
31 30
F G H I
M
J
P
K M N L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15 +0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX. INCHES 0.9290.016 0.795 +0.009 -0.008 0.551 +0.009 -0.008 0.6930.016 0.031 0.024 0.012 +0.004 -0.005 0.006 0.026 (T.P.) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 +0.005 -0.004 0.0040.004 55 0.119 MAX. P100GF-65-3BA1-3
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
Remark The external dimensions and material of the ES version are the same as those of the mass-produced version.
42
Data Sheet U14118EJ1V0DS
PD78F4938A
9. RECOMMENDED SOLDERING CONDITIONS
The PD78F4938A should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 9-1. Surface Mounting Type Soldering Conditions
PD78F4938AGF-3BA: 100-pin plastic QFP (14 x 20)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-207-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 20 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 20 hours) Solder bath temperature: 260C max., Time: 10 seconds max., Count: once, Preheating temperature: 120C max. (package surface temperature), Exposure limit: 7 daysNote (after that, prebake at 125C for 20 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-207-2
Wave soldering
WS60-207-1
Partial heating
-
Note
After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
Data Sheet U14118EJ1V0DS
43
PD78F4938A
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD78F4938A. Also refer to (5) Cautions on using development tools. (1) Language processing software
RA78K4 CC78K4 DF784937 CC78K4-L Assembler package common to 78K/IV Series C compiler package common to 78K/IV Series Device file for PD784938A Subseries C compiler library source file common to 78K/IV Series
(2) Flash memory writing tools
Flashpro III (PG-FP3) FA-100GF Flash programmer for microcontroller with on-chip flash memory
Flash memory writing adapter for 100-pin plastic QFP (GF-3BA type). Wiring must be performed according to the product used.
(3) Debugging tools * When IE-78K4-NS in-circuit emulator is used
IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C IE-70000-CD-IF-C IE-70000-PC-IF-C IE-784937-NS-EM1 NP-100GF EV-9200GF-100 ID78K4-NS SM78K4 DF784937 In-circuit emulator common to 78K/IV Series Power supply unit for IE-78K4-NS Interface adapter used when PC-9800 series (except notebook type) is used as host machine PC card and cable used when PC-9800 series notebook type PC is used as host machine Interface adapter used when IBM PC/ATTM or compatible is used as host machine Emulation board to emulate PD784938A Subseries Emulation probe for 100-pin plastic QFP (GF-3BA type) Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) Integrated debugger for IE-78K4-NS System simulator common to 78K/IV Series Device file for PD784938A Subseries
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Data Sheet U14118EJ1V0DS
PD78F4938A
* When IE-784000-R in-circuit emulator is used
IE-784000-R IE-70000-98-IF-B IE-70000-98-IF-C IE-70000-98N-IF IE-70000-PC-IF-B IE-70000-PC-IF-C IE-78000-R-SV3 IE-784937-NS-EM1 IE-784000-R-EM IE-78K4-R-EX2 In-circuit emulator common to 78K/IV Series Interface adapter used when PC-9800 series (except notebook type) is used as host machine
Interface adapter and cable used when PC-9800 series notebook type PC is used as host machine Interface adapter used when IBM PC/AT or compatible is used as host machine
Interface adapter and cable used when EWS is used as host machine Emulation board to emulate PD784938A Subseries Emulation board common to 78K/IV Series Emulation probe conversion board necessary when using IE-784937-NS-EM1 on IE-784000-R. Not necessary when using IE-784937-R-EM1 Emulation probe for 100-pin plastic QFP (GF-3BA type) Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) Integrated debugger for IE-784000-R System simulator common to 78K/IV Series Device file for PD784938A Subseries
EP-78064GF-R EV-9200GF-100 ID78K4 SM78K4 DF784937
(4) Real-time OS
RX78K/IV MX78K4 Real-time OS for 78K/IV Series OS for 78K/IV Series
Data Sheet U14118EJ1V0DS
45
PD78F4938A
(5) Cautions on using development tools * The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784937. * The CC78K4 and RX78K/IV are used in combination with the RA78K4 or DF784937. * The Flashpro III, FA-100GF, and NP-100GF are products made by Naito Densei Machida Mfg. Co, Ltd (TEL +81-44-822-3813). * The host machine and OS suitable for each software are as follows:
Host Machine [OS] PC PC-9800 series [Windows] IBM PC/AT and compatibles [Japanese/English Windows] Note Note Note Note EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] NEWSTM (RISC) [NEWS-OSTM] -- --
Software RA78K4 CC78K4 ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
Note
DOS-based software
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Data Sheet U14118EJ1V0DS
PD78F4938A
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. * Documents related to devices
Document Name Document No. Under preparation This document U13987E U10905E U10095E
PD784935A, 784936A, 784937A, 784938A Data Sheet PD78F4938A Data Sheet PD784938 Subseries User's Manual Hardware
78K/IV Series User's Manual Instructions 78K/IV Series Application Note Software Basics
* Documents related to development tools (user's manuals)
Document Name RA78K4 Assembler Package Language Operation Structured Assembler Preprocessor CC78K4 C Compiler Language Operation PG-FP3 Flash Memory Programmer IE-78K4-NS IE-784000-R IE-784937-R-EM1 IE-784937-NS-EM1 EP-78064 SM78K4 System Simulator Windows Based SM78K Series System Simulator Reference External Part User Open Interface Specifications Reference Reference U11571E U11572E U13502E U13556E U12903E To be prepared To be prepared EEU-1469 U10093E U10092E Document No. U11162E U11334E U11743E
ID78K4 Integrated Debugger Windows Based ID78K4-NS Integrated Debugger Windows Based Project Manager Ver. 3.12 or Later Windows Based
U10440E U12796E U14610E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U14118EJ1V0DS
47
PD78F4938A
* Documents related to embedded software (user's manuals)
Document Name 78K/IV Series Real-Time OS Fundamental Installation Document No. U10603E U10604E
* Other documents
Document Name SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769X C10535E C11531E U10983E C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
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Data Sheet U14118EJ1V0DS
PD78F4938A
[MEMO]
Data Sheet U14118EJ1V0DS
49
PD78F4938A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
EEPROM, FIP, and IEBus are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation.
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Data Sheet U14118EJ1V0DS
PD78F4938A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
J01.2
Data Sheet U14118EJ1V0DS
51
PD78F4938A
* The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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